The present invention relates to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a vertical channel type nonvolatile memory device and a method for fabricating the same.
Memory devices are classified into volatile memory devices and nonvolatile memory devices according to whether data is retained when power is interrupted. Volatile memory devices lose data when power is interrupted. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). In contrast, nonvolatile memory devices retain stored data even when power is interrupted. Examples of nonvolatile memory devices include flash memory.
Nonvolatile memory devices are classified into floating gate type nonvolatile memory devices and charge trap type nonvolatile memory devices according to data storing methods.
A floating gate type nonvolatile memory device includes a plurality of memory cells, each of which has a tunnel insulation layer, a floating gate electrode, a charge blocking layer, and a control gate electrode being formed over a substrate. The floating gate type nonvolatile memory device stores data by accumulating charges within a conduction band of the floating gate electrode.
A charge trap type nonvolatile memory device includes a plurality of memory cells, each of which has a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a control gate electrode being formed over a substrate. The charge trap type nonvolatile memory device stores data by trapping charges in a deep-level trap site within the charge trap layer.
However, planar nonvolatile memory devices fabricated in a single layer over a silicon substrate have limitations in improving integration density due to fine pattern formation as patterning technologies have reached limitations in some aspects.
Therefore, there have been proposed vertical channel type nonvolatile memory devices in which strings are vertically arranged over a substrate. A vertical channel type nonvolatile memory device includes a lower selection transistor, a plurality of memory cells, and an upper selection transistor, which are sequentially formed over a substrate. The vertical channel type nonvolatile memory device can improve integration density because the strings are arranged vertically over the substrate.
Hereinafter, a conventional method for fabricating a vertical channel type nonvolatile memory device will be described with reference to the accompanying drawings.
FIGS. 1A to 4B are exemplary diagrams illustrating a conventional method for fabricating a vertical channel type nonvolatile memory device. For the sake of convenience, a description about a process of forming a lower selection transistor and an upper selection transistor is omitted, and the following description will be focused on a process of forming a plurality of memory cells. In particular, figures “A” are cross-sectional views illustrating intermediate results, and figures “B” are plan views at height A-A′ of figures “A”.
Referring to FIGS. 1A and 1B, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for gate electrode are alternately formed over a substrate 10 where a lower structure including a source line, a lower selection transistor, and the like is formed. The interlayer dielectric layers 11 and the conductive layers 12 are selectively etched to form a plurality of contact holes H exposing the substrate 10.
Referring to FIGS. 2A and 2B, a charge blocking layer 13 is formed on inner walls of the contact holes H. The charge blocking layer 13 prevents charges from passing through the charge trap layer 14 and moving toward the gate electrode.
A charge trap layer 14 is formed over the charge blocking layer 13. The charge trap layer 14 traps charges in a deep-level trap site and serves as a substantial data storage. The charge trap layer 14 is formed of nitride.
A tunnel insulation layer 15 is formed within the contact holes H in which the charge blocking layer 13 and the charge trap layer 14 are formed. The tunnel insulation layer 15 serves as an energy barrier layer because of tunneling of charges.
Referring to FIGS. 3A and 3B, a center region of the tunnel insulation layer 15 is etched to form openings for channel which expose the substrate 10. The openings for channel are filled with a layer for channel to form a plurality of channels 16 protruding from the substrate 10.
Referring to FIGS. 4A and 4B, a plurality of mask patterns (not shown) are formed over a resulting structure where the channels 16 are formed. The plurality of mask patterns cover a region for memory cells MC and extend in a first direction I-I′. Using the mask patterns as an etch barrier, the interlayer dielectric layer 11 and the conductive layer 12 for gate electrode are etched to form a plurality of gate electrodes 12A. The etched region is filled with an insulation layer 17.
In this way, a plurality of memory cells MC each including the tunnel insulation layer 15, the charge trap layer 14, the charge blocking layer 13, and the gate electrode surrounding the outer surface of the vertical channel 16 are formed. At this point, the memory cells MC stacked along the same channel 16 constitute one string. In addition, the memory cells MC connected to the gate electrode 12A (memory cells arranged in the first direction I-I′) operate as one page. That is, a plurality of memory cells MC formed in each layer operate as a plurality of pages.
FIG. 5 is a perspective view explaining a process of forming word lines in the conventional vertical channel type nonvolatile memory device.
Referring to FIG. 5, the interlayer dielectric layers 11 and the gate electrodes 12A are patterned to expose the gate electrodes 12A of the memory cells stacked along the channels 16. Word lines 18 connected to the gate electrodes of the memory cells are formed.
As described above, since the plurality of memory cells formed on the same layer operate as the plurality of pages, the word lines 18 must be formed in each page even though the gate electrodes 12A are formed on the same layer.
According to the prior art, the channels 16 are formed after forming the conductive layers 12 for gate electrode, the charge blocking layer 13, the charge trap layer 14, and the tunnel insulation layer 15. That is, since the fabrication process of the vertical channel type nonvolatile memory device is performed in reverse order of that of the planar nonvolatile memory device, the characteristics of the memory device are degraded, which will be described hereinafter in more detail.
First, degradation in the layer quality of the tunnel insulation layer 15 causes degradation in date retention characteristic and reliability. Since the nonvolatile memory device stores and erases data by using Fowler-Nordheim (F-N) tunneling, the layer quality of the tunnel insulation layer 15 serving as the energy barrier in the F-N tunneling has a great influence on the characteristics of the memory device.
However, the layer quality of the tunnel insulation layer 15 is degraded because the tunnel insulation layer 15 is formed at the last time and the openings for channel are formed by etching the center region of the tunnel insulation layer 15.
Second, since the channels 16 formed of polysilicon are formed in order to prevent damage of the charge blocking layer 13, the charge trap layer 14, and the tunnel insulation layer 15 in a process of forming the layer for channel within the openings, the current flow in the channels 16 is lowered and the uniformity of a threshold voltage distribution is degraded.
A single crystal silicon growth process is typically performed using a silicon source gas and an HCl gas at high temperature. The silicon source gas supplies silicon source for growing single crystal silicon, and removes a natural oxide layer formed on the substrate 10 through an oxidation-reduction reaction, or removes silicon deposited on the insulation layer, thereby growing single crystal silicon only on the surface of the substrate 10.
If the single crystal silicon growth process is applied to the process of forming the channels 16 of the conventional vertical channel type nonvolatile memory device, the charge blocking layer 13, the charge trap layer 14, and the tunnel insulation layer 15 are damaged. Therefore, there is a difficulty in forming the channels 16 of single crystal silicon.
Meanwhile, since the tunnel insulation layer 15, the charge trap layer 14, the charge blocking layer 13, and the gate electrode are formed to surround the outer surface of the channel 16, one string ST is formed with respect to one channel 16. Therefore, there is a limitation in increasing the integration density of the nonvolatile memory device.
Furthermore, it is necessary to form the word lines 18 at each page with respect to the gate electrodes 12A formed on each layer. Thus, an area for formation of the word lines 18 at each page is required and thus there is another limitation in increasing the integration density of the memory device.